Introduction
In previous discussions, we explored the PSRR parameter of LDOs (Low Dropout Regulators) and the impact of peripheral circuits on their ripple rejection performance. Beyond PSRR, stability design is another critical aspect of LDO performance. This article delves into LDO stability, focusing on loop compensation techniques to ensure reliable operation.
Types of Linear Power Supplies
Traditional Linear Regulators
- Uses a PNP transistor to drive an NPN pass transistor.
- Requires a minimum dropout voltage (1.5V–2.5V) between input and output, limiting efficiency in battery-powered applications.
Low Dropout Regulators (LDOs)
- Employs a PNP pass transistor, reducing dropout voltage to Vsat (saturation voltage).
Advantages:
- Dropout as low as 10–20mV under light loads.
- Improved battery life due to lower power dissipation.
Quasi-LDOs
- Hybrid structure with an NPN pass transistor and PNP driver.
- Dropout voltage between traditional regulators and LDOs.
PMOS-Based LDOs
- Uses a P-MOSFET as the pass element.
Benefits:
- Extremely low dropout voltage.
- Minimal drive current loss.
- Supports high-current applications in compact packages.
LDO Stability Analysis
Stability Criteria
- A negative feedback system must maintain phase margin > 45° at the 0dB crossover frequency.
- Key challenge: High output impedance of LDOs introduces low-frequency poles, risking instability.
Pole-Zero Distribution
- Load Pole (PL): Formed by load resistance and output capacitance (e.g., 159Hz at 50mA load).
- Integrator Pole (P1): Internal compensation (~1kHz).
- Power Stage Pole (Ppwr): High-frequency pole (~500kHz).
Uncompensated LDO Issues:
- Phase shift approaches 180° at crossover (~40kHz), causing oscillation.
Loop Compensation Techniques
ESR Zero Compensation
- Output capacitor ESR introduces a zero to counteract pole-induced phase lag.
Zero frequency:
f_ZESR = 1 / (2π × ESR × Cout)
Effect of ESR:
- Optimal ESR: Balances bandwidth and phase margin (e.g., 70° at 100kHz).
- Excessive ESR: Raises bandwidth beyond Ppwr, reducing phase margin (risk of oscillation).
- Too Low ESR: Zero ineffective at crossover frequency (e.g., 5mΩ ESR shifts zero to 14MHz).
Output Capacitor Selection
Tantalum Capacitors:
- Moderate ESR (~500mΩ).
- Stable across temperatures.
MLCCs:
- Ultra-low ESR (<10mΩ).
- Only suitable for MLCC-optimized LDOs (e.g., MIC5235).
Example:
- MIC29302 (Non-MLCC LDO): Requires ESR > 500mΩ (3Ω max) for stability.
- MIC5235 (MLCC-Compatible): Stable with ESR as low as 5mΩ.
Simulation Results
Case 1: MLCC-Optimized LDO (MIC5235)
| ESR (Ω) | Bandwidth (kHz) | Phase Margin (°) |
|---------|------------------|-------------------|
| 0.005 | 40 | 57 |
| 3 | 114 | 94 |
| 10 | 305 | 60 |
Key Insight: Higher ESR improves stability but must stay within manufacturer limits.
Case 2: Non-MLCC LDO (MIC29302)
| ESR (Ω) | Bandwidth (kHz) | Phase Margin (°) |
|---------|------------------|-------------------|
| 0.5 | 72 | 67 |
| 0.005 | 47 | 3 |
| 5 | 453 | 75 |
Key Insight: Low ESR (MLCC) destabilizes non-optimized LDOs.
FAQs
Q1: Why does ESR affect LDO stability?
A: ESR creates a zero that counters phase lag from poles, boosting phase margin.
Q2: Can I use ceramic capacitors (MLCCs) with any LDO?
A: Only if the LDO is designed for MLCCs (e.g., internal compensation for low ESR).
Q3: What happens if ESR is too high?
A: Excess ESR shifts bandwidth near Ppwr, risking high-frequency oscillation.
👉 Learn more about LDO stability
Conclusion
- LDO stability hinges on pole-zero management via output capacitor ESR.
- MLCCs demand specialized LDO designs; tantalum capacitors suit conventional LDOs.
- Simulation tools (e.g., SPICE) validate compensation strategies before prototyping.
For further reading, explore AN-1482 (TI) on LDO stability with ceramic capacitors.